1. Field of the Invention
The present invention relates to a test mode device for monitoring an operation of an internal address counter, and more specifically, to a technique for regulating a pulse width and a pulse generating time of an address strobe signal to cope with a column fail of the dynamic random access memory (DRAM).
2. Description of the Prior Art
As the operating speed (e.g., clock frequency) of a DRAM increases above a threshold, operations that receive a command signal or an address signal inputted externally frequently fail.
Generally, when an external clock signal of a DRAM transitions, an internal clock signal generated by the external clock signal also transitions. However, as the clock speed tCK (frequency) of the DRAM becomes higher, the internal clock signal does not transition at the same time the external clock signal transitions. As a result, the DRAM does not receive an external address properly. This event is called a column fail.
Conventionally, a method for regulating a pulse width of an internal clock signal CLKP4 generated by an external clock signal CLK is used in order to solve the column fail problem.
An address strobe signal EXTYP8 and a read/write strobe signal are generated from a pulse signal of the internal clock signal CLKP4.
As a result, if the pulse width of the internal clock signal CLKP4 is regulated in order to adjust the pulse width of the address strobe signal EXTYP8, the pulse width of the read/write strobe signal is also adjusted.
If the pulse width of the address strobe signal EXTYP8 is regulated, the pulse widths of relevant signals are simultaneously changed. As a result, there is a limit to the improvement of DRAM performanceachievable using this conventional method.
FIG. 1 is a timing diagram illustrating the mis-operation of a conventional address counter circuit. If a pulse width of an internal clock signal changes, a pulse width of the address strobe signal EXTYP8 is also adjusted, which results in the mis-operation of the conventional address counter circuit.
As shown in FIG. 1, if an external clock signal CLK is inputted, an internal clock signal CLKP4 is generated by the external clock signal CLK, and then an address strobe signal EXTYP8 is generated. Internal addresses ADD_EV<1> and ADD_OD<1> are generated by the address strobe signal EXTYP8. Here, the regulated pulse width of the internal clock signal CLK is also applied to the address strobe signal EXTYP8.
After an external address signal ADD<0> transitions from a high to a low level, the address strobe signal EXTYP8 having the longer pulse width is maintained at a high level for a predetermined time and then transitions to a low level.
Though the external address signal ADD<0> and the address strobe signal EXTYP8 are required to be within a cycle of the external clock signal CLK, they are out of cycle with the external clock signal CLK because the pulse width of the address strobe signal EXTYP8 is lengthened.
As a result, the address strobe signal EXTYP8 is maintained at the high level for a predetermined time (A, B, C) and transitions to the low level after the external address signal ADD<0> transitions from the high to low level.
For the predetermined time (A, B, C), the DRAM accesses a wrong address, thereby generating a mis-operation.